Build android snapdragon

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Revision as of 19:22, 19 March 2023 by Mark (talk | contribs) (Created page with "== InForce == pulling all src and apply patches ./fetchsrc_and_build.sh Build... sudo apt-get install openjdk-8-jdk cd /home/mhamilton/projects/snapdragon/InForce/Inforce-IFC6601-AndroidBSP-880457-Rel-v2.1/source/LA.UM.5.5.r1-04300-8x96.0_Rel_V2.1 source build/envsetup.sh lunch msm8996-userdebug make -j 6 == New process from Kynetics == may need to do this: git config --global http.sslVerify false curl https://storage.googleapis.com/git-repo-downloads/re...")
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InForce[edit | edit source]

pulling all src and apply patches

./fetchsrc_and_build.sh 

Build...

sudo apt-get install openjdk-8-jdk
cd /home/mhamilton/projects/snapdragon/InForce/Inforce-IFC6601-AndroidBSP-880457-Rel-v2.1/source/LA.UM.5.5.r1-04300-8x96.0_Rel_V2.1
source build/envsetup.sh
lunch msm8996-userdebug
make -j 6

New process from Kynetics[edit | edit source]

may need to do this:

git config --global http.sslVerify false
curl https://storage.googleapis.com/git-repo-downloads/repo > ~/bin/repo
chmod a+x ~/bin/repo
repo init -u https://bitbucket.org/heuresisandroidos/platform-manifest.git -b heuresis/LA.UM.6.5.r1-06000-8x96.0 -m Heuresis-LA.UM.6.5.r1-06000-8x96.0.xml --repo-url=git://codeaurora.org/tools/repo.git --repo-branch=aosp-new/stable
repo sync -c --no-clone-bundle
tar -xzvf proprietary.tar.gz -C vendor/qcom/
source build/envsetup.sh
lunch hbi160-userdebug
export LC_ALL=C
make -j8
make -j8 otapackage
make -j8 updatepackage

The last is the flash update package.

Now updating to a new branch (kernel)

repo init -b viken/LA.UM.6.5.r1-06000-8x96.0 -m Viken-LA.UM.6.5.r1-06000-8x96.0.xml --repo-url=git://codeaurora.org/tools/repo.git --repo-branch=aosp-new/stable
repo sync kernel/msm-3.18/

Had to run one more command

repo sync device/viken

I2C bus config info[edit | edit source]

The dtsi file is located:

kernel/msm-3.18/arch/arm/boot/dts/qcom/apq8096-hbi160.dtsi

I2c-10 is set to 100k baud rate. This should be the location of the summing box fpga at address 0x55.

Just added the following parameters to the dtsi file making the duty cycle actually 50% not 30% @100kHz based on the default settings.

/* modified from standard values
   fs-clk-div = 124
   high-time-clk-div = 62
   The following values where determined empirically to achieve a 50%
   duty cycle on the clk.
   */
qcom,fs-clk-div = <90>;
qcom,high-time-clk-div = <93>;
/* 0x0 – Legacy mode
   0x01 – One cycle wide low pulse is rejected
   0x2 – Two cycles wide low pulse is rejected
   0x3 – Three cycles wide low pulse is rejected
   */
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;