Xrf spi debug

Spi communications during System Check (Shutter Cal)

CalibrateDetector function is main loop that runs the shutter cal process. It does a bunch of memory allocations, close_shutter calls and it calls InitShaperXL3. After this the filter wheel will be moved to the correct position and the xray tube will be started. Now we start SpectraView2_segger and drop into the looping function GetSpectra which is the function that reads data from the fpga and determines when the process is done.

Setting of Shapers

InitShaperXL3 sets up a local structure with shaper parameters based on the current detector being used. This function also calls adjustDetectorShapers and SetShaperXL3. This function then terminates.

adjustDetectorShapers modify's some of the parameters based on a few more conditions. Why this is not included in the previous function is beyond me... All parameters are in system ram, still nothing has been updated in the actual fpga registers.

SetShaperXL3 makes some addition modifications to parameters and creates a few new ones based on other but with additional offsets (wtf), it then calls SetShaperUsingSPI. There is also the ability to debug output a collection of probably important parameters: <pre> sprintf(buf,"SLOW_RISE_TIME:%d\r\n",SHS.SLOW_RISE_TIME); sprintf(buf,"GATE_RECOVERY:%d\r\n",SHS.GATE_RECOVERY); sprintf(buf,"RTD_RISE_TIME:%d\r\n",SHS.RTD_RISE_TIME); sprintf(buf,"RTD_FLAT_TOP_RTM:%d\r\n",SHS.RTD_FLAT_TOP_RTM); sprintf(buf,"PEAK_TIME:%d\r\n",SHS.PEAK_TIME); sprintf(buf,"AFTER_PEAK_GUARD:%d\r\n",SHS.AFTER_PEAK_GUARD); sprintf(buf,"DT_EXTENSION:%d\r\n",SHS.DT_EXTENSION); sprintf(buf,"SLOW_EXTENSION:%d\r\n",SHS.SLOW_EXTENSION); sprintf(buf,"FAST_EXTENSION:%d\r\n",SHS.FAST_EXTENSION); sprintf(buf,"SLOW_BIN_GAIN:%d\r\n",SHS.SLOW_BIN_GAIN); sprintf(buf,"SLOW_FINE_GAIN:%d\r\n",SHS.SLOW_FINE_GAIN); </pre>

SetShaperUsingSPI, I found something that actually writes stuff to the fpga. We start off reading REG_ADDR_2 and clearing bit 8.

<pre> usDetector = Read_Single ( (REG_ADDR_2) ); usDetector &= ~(1<<8); // First detector

Write_Single( (REG_ADDR_2),usDetector ); Write_Single( (REG_ADDR_17),SHS.GATE_WIDTH_EXT); Write_Single( (REG_ADDR_18),SHS.GATE_RECOVERY); Write_Single( (REG_ADDR_16),SHS.ADC_OFFSET); Write_Single( (REG_ADDR_19),SHS.FAST_RISE_TIME +256*(SHS.FAST_RISE_TIME+SHS.FAST_FLAT_TOP))  ;

if (SHS.CUSP_TRAP) { usReg7 = ((short)(SHS.SLOW_FLAT_TOP))|0x8000; } else { usReg7 = ((short)(SHS.SLOW_FLAT_TOP))&0x7FFF; }

//bits 12 to 10 which have been moved to a new register Reg 31

    Write_Single( (REG_ADDR_20), usReg7);	
    Write_Single( (REG_ADDR_21) ,SHS.SLOW_RISE_TIME);         
    Write_Single( (REG_ADDR_22) ,SHS.SLOW_EXTENSION + 256*SHS.FAST_EXTENSION);// check it with the old one and send
    Write_Single( (REG_ADDR_23),SHS.FAST_THRESH_LOW);
    Write_Single( (REG_ADDR_24),SHS.FAST_THRESH_HIGH);
    Write_Single( (REG_ADDR_25),SHS.SLOW_THRESH_LOW);
    Write_Single( (REG_ADDR_26),SHS.SLOW_THRESH_HIGH);     
    Write_Single( (REG_ADDR_27),SHS.SLOW_BLR_TAU + 256*SHS.FAST_BLR_TAU); 
    Write_Single( (REG_ADDR_28),SHS.AFTER_PEAK_GUARD );
    Write_Single( (REG_ADDR_29),SHS.PEAK_TIME);   
    Write_Single( (REG_ADDR_30),FPGA_GAIN);        // for gain control (00->gain=1.05, 01 ->gain=2, 02 -> gain=4) 
    Write_Single( (REG_ADDR_31),SHS.SLOW_BIN_GAIN);     
    Write_Single( (REG_ADDR_32),SHS.SLOW_FINE_GAIN); 
    Write_Single( (REG_ADDR_33),SHS.DT_EXTENSION);	

1. if 1//def RTD

  usReg34 = SHS.RTD_RISE_TIME;
   Write_Single(REG_ADDR_34, usReg34);// Setting the RTD RISE TIME
   usReg35 = SHS.RTD_FLAT_TOP_RTM;//usReg34 + ( usReg19 & 0xFF) + ( usReg19/256 );
   Write_Single(REG_ADDR_35, usReg35);

1. endif

   //Clear Spectrum is optional here

ClearSpectrum_SPI ( );

   usTempData =  Read_Single ( (REG_ADDR_2) );
   usTempData &= ~0x0002; //Disable acquisition
   Write_Single ( (REG_ADDR_2), usTempData ); 
   
   usTempData =  Read_Single ( (REG_ADDR_2) );
   usTempData |= (1<<7); //Enable RTD

  Write_Single ( (REG_ADDR_2), usTempData | 0x0000 );// This selects Slow Shaper at the output of the DAC board - default

</pre>

Getting spectra

Ok, so we start by disabling spectral acquisition startSpectrum(FALSE) and then call InitShaperXL3. We then zero out localSpecra buffer, initialize a bunch of local variables and get the current (starting) realtime and livetime values for future use.

Register definitions

register	description
REG_ADDR_0	Frequency value (set to 9?) Might readback some testscope2 block data
REG_ADDR_1	Delay value (set to 20?), bit 15 something to do with scope data
REG_ADDR_2	shaper control
	bit 11 unused, bit 10 rtd shaper enable, bit 9 slow shaper enable, bit 8 fast shaper enable
	bit 7 rtd enable, bit 6 unused, bit 5 unused, bit 4 start timer (appears to be disconnected in 8474)
	bit 3 unused, bit 2 unused, bit 1 enable acquisition (and timers), bit 0 reset blr
REG_ADDR_3	Revision register (DD[3][15..0]
REG_ADDR_4	Live Time LSB <code>GetCurrentRealAndLiveTime</code> Pulse processor state machine is halted until these are non-zero. These values should be initialized to 0xffff and this will allow the pulse processor to run. (countdown).
REG_ADDR_5	Live Time MSB <code>GetCurrentRealAndLiveTime</code> Pulse processor state machine is halted until these are non-zero. These values should be initialized to 0xffff and this will allow the pulse processor to run. (countdown).
REG_ADDR_6	Real Time LSB <code>GetCurrentRealAndLiveTime</code> Pulse processor state machine is halted until these are non-zero. These values should be initialized to 0xffff and this will allow the pulse processor to run. (countdown).
REG_ADDR_7	Real Time MSB <code>GetCurrentRealAndLiveTime</code> Pulse processor state machine is halted until these are non-zero. These values should be initialized to 0xffff and this will allow the pulse processor to run. (countdown).
REG_ADDR_8	Live Time LSB <code>GetRealAndLiveTime</code> (latched values)
REG_ADDR_9	Live Time MSB <code>GetRealAndLiveTime</code> (latched values)
REG_ADDR_10	Real Time LSB <code>GetRealAndLiveTime</code> (latched values)
REG_ADDR_11	Real Time MSB <code>GetRealAndLiveTime</code> (latched values)
REG_ADDR_12	Current fast value (read only)
REG_ADDR_13	Current slow value (read only)
REG_ADDR_14	unused
REG_ADDR_15	unused
REG_ADDR_16	adc offset
REG_ADDR_17	gate width extension
REG_ADDR_18	gate recovery
REG_ADDR_19	bits 0-7 fast rise time, bits 8-15 fast flat top + fast rise time
REG_ADDR_20	bit 15 cusp trap, 0-14 slow flat top
REG_ADDR_21	slow rise time
REG_ADDR_22	bits 0-7 slow extension, bits 8-15 fast extension
REG_ADDR_23	fast threshold low, typically set to 1.5*current fast value
REG_ADDR_24	fast threshold high, typically set to 2.0*current fast value
REG_ADDR_25	slow threshold low, typically set to 1.5*current slow value
REG_ADDR_26	slow threshold high, typically set to 2.0*current slow value
REG_ADDR_27	bits 0-7 slow blr tau, bits 8-15 fast blr tau
REG_ADDR_28	after peak guard
REG_ADDR_29	peak time
REG_ADDR_30	fpga gain, gain control (00->gain=1.05, 01 ->gain=2, 02 -> gain=4)
REG_ADDR_31	slow bin gain
REG_ADDR_32	slow fine gain
REG_ADDR_33	dt extension
REG_ADDR_34	rtd rise time
REG_ADDR_35	rtd flat top rtm
REG_ADDR_36	bit 0 Bank select (0=bank_0, 1=bank_1), bit 1 clear on read (0=clear, 1=no clear)
REG_ADDR_37
REG_ADDR_38
REG_ADDR_39
REG_ADDR_40
REG_ADDR_41
REG_ADDR_42
REG_ADDR_43
REG_ADDR_44
REG_ADDR_45
REG_ADDR_46
REG_ADDR_47
REG_ADDR_48
REG_ADDR_49
REG_ADDR_50
REG_ADDR_51
REG_ADDR_52
REG_ADDR_53
REG_ADDR_54
REG_ADDR_55
REG_ADDR_56
REG_ADDR_57
REG_ADDR_58
REG_ADDR_59
REG_ADDR_60
REG_ADDR_61
REG_ADDR_62
REG_ADDR_63
REG_ADDR_64
REG_ADDR_65
REG_ADDR_66
REG_ADDR_67
REG_ADDR_68
REG_ADDR_69

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