Snapdragon: Difference between revisions

From SoftwareGuy
Jump to navigation Jump to search
Mark (talk | contribs)
No edit summary
Mark (talk | contribs)
Line 429: Line 429:
  remotes/m/heuresis/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/heuresis/LA.UM.6.5.r1-06000-8x96.0_Rel_V3.0
  remotes/m/heuresis/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/heuresis/LA.UM.6.5.r1-06000-8x96.0_Rel_V3.0
  remotes/m/viken/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/viken/LA.UM.6.5.r1-06000-8x96.0
  remotes/m/viken/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/viken/LA.UM.6.5.r1-06000-8x96.0
=== bootanimation ===
Make the jpg's
fmpeg -i ../Raven-splash-091624.mp4 -vf fps=30 -s 720x405 out%d.jpg
edit the desc.txt file
720 405 30
p 1 0 part0 FFFFFF
zip the animation
zip -r0 bootanimation.zip part0 desc.txt
copy to kernel location
cp bootanimation.zip /mnt/data/projects/snap/device/viken/harrier


== Snapdragon target board ==
== Snapdragon target board ==

Revision as of 10:38, 17 September 2024

cd projects/snapdragon/ERAGON820_Android-MM-BSP_Relv2.0/source
bash ./ERAGON820_fetchsrc_and_build.sh

(choose ufs)

cd /home/mhamilton/projects/snapdragon/ERAGON820_Android-MM-BSP_Relv2.0/source/LA.HB.1.3.2-16800-8x96.0_Relv2.0 
~/bin/repo sync -c --no-clone-bundle (username mhamilton01, password GhaKskZvphZNQPndC7JJ) bitbucket app password setting
source build/envsetup.sh 
lunch msm8996-userdebug 
lunch harrier-userdebug 
make -j 12

Latest Ubuntu uses python3, to make the build work switch to python2 (as of 9/10/2024).

sudo ln -sf /usr/bin/python2 /usr/bin/python
sudo ln -sf /usr/bin/python3 /usr/bin/python

Then switch back...

Next we have the jack-server error. Edit the following file: Remove TLSv1, TLSv1.1 from jdk.tls.disabledAlgorithms in /etc/java-8-openjdk/security/java.security file

Now ps -aux | grep jack and kill the jack server.

Mods

art/build/Android.common_build.mk

# Host.
ART_HOST_CLANG := false
ifneq ($(WITHOUT_HOST_CLANG),true)
  # By default, host builds use clang for better warnings.
  ART_HOST_CLANG := true
endif

To this:

# Host.
ART_HOST_CLANG := false
ifeq ($(WITHOUT_HOST_CLANG),false)
  # By default, host builds use clang for better warnings.
  ART_HOST_CLANG := true
endif

Maybe this:

cp /usr/bin/ld.gold prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.6/x86_64-linux/bin/ld

Code, where stuff is...

Splash screens

Kernel splash screen is in "kernel/msm-3.18/drivers/video/msm/mdss/splash.h". Android splash screen is in "device/viken/common/overlay/frameworks/base/core/res/assets/images/android-logo-mask.png" and "device/viken/common/overlay/frameworks/base/core/res/assets/images/android-logo-shine.png".

mipi

find . -name *mipi*
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi_autopll_20nm.c
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi_autopll.c
./bootable/bootloader/lk/platform/msm_shared/include/mipi_dsi.h
./bootable/bootloader/lk/platform/msm_shared/include/mipi_dsi_autopll_thulium.h
./bootable/bootloader/lk/platform/msm_shared/include/mipi_dsi_i2c.h
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi_i2c.c
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi_phy.c
./bootable/bootloader/lk/platform/msm_shared/mipi_dsc.c
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi.c
./bootable/bootloader/lk/platform/msm_shared/mipi_dsi_autopll_thulium.c
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_phy.o
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsc.o
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi.d
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_autopll_thulium.d
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsc.d
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_autopll_thulium.o
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_i2c.d
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_i2c.o
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi.o
./out/target/product/msm8996/obj/EMMC_BOOTLOADER_OBJ/build-msm8996/platform/msm_shared/mipi_dsi_phy.d
./kernel/Documentation/devicetree/bindings/media/samsung-mipi-csis.txt
./kernel/Documentation/devicetree/bindings/mipi
./kernel/Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
./kernel/Documentation/devicetree/bindings/mipi/nvidia,tegra114-mipi.txt
./kernel/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-jdi-dualmipi-cmd.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-jdi-4k-dualmipi-video.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-video.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-jdi-4k-dualmipi-video-nofbc.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-jdi-dualmipi-video.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
./kernel/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-cmd.dtsi
./kernel/include/drm/drm_mipi_dsi.h
./kernel/include/linux/platform_data/lcd-mipid.h
./kernel/include/video/mipi_display.h
./kernel/include/video/exynos_mipi_dsim.h
./kernel/include/video/sh_mipi_dsi.h
./kernel/drivers/gpu/drm/drm_mipi_dsi.c
./kernel/drivers/gpu/drm/tegra/mipi-phy.c
./kernel/drivers/gpu/drm/tegra/mipi-phy.h
./kernel/drivers/gpu/host1x/mipi.c
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi_common.h
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi_lowlevel.c
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi_lowlevel.h
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi_regs.h
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi.c
./kernel/drivers/video/fbdev/exynos/exynos_mipi_dsi_common.c
./kernel/drivers/video/fbdev/sh_mipi_dsi.c
./kernel/drivers/video/fbdev/omap/lcd_mipid.c
./kernel/drivers/phy/phy-exynos-mipi-video.c
./kernel/drivers/media/platform/exynos4-is/mipi-csis.h

Docs

kernel/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt

Driver

kernel/drivers/video/msm/mdss/mdss_dsi_panel.c

Also look at mdss_dsi.c

Parser. Just found this parser for generating the display params. I like it when other people think like me...

device/qcom/common/display/tools/parser.pl:

So, I'm not sure when the input xml file comes from. Maybe I'm not so happy...

clk list

The list_clks.sh tool is located at device/qcom/common/tools/list_clks.sh

root@msm8996:/ # sh /sdcard/list_clks.sh -d /sys/kernel/debug -v 1           
Verbosity: 1
Root Debug Dir: /sys/kernel/debug
                                Local       Enabled     Rate        Measured Rate
aggre1_noc_a_clk                N           ON          1000        
aggre1_noc_clk                  N           ON          1000        
aggre2_noc_a_clk                N           ON          1000        
aggre2_noc_clk                  N           ON          1000        
ahb_clk_src                     Y           ON          19200000    
alpha_xo_ao                     Y           ON          19200000    
audio_ext_ap_clk                Y           OFF         0           
audio_ext_ap_clk2               Y           OFF         0           
audio_ext_lpass_mclk            Y           OFF         0           
audio_ext_lpass_mclk2           Y           OFF         0           
audio_ext_pmi_clk               Y           OFF         0           
bb_clk1                         N           OFF         1000        
bb_clk1_ao                      N           OFF         1000        
bb_clk1_pin                     N           OFF         1000        
bb_clk1_pin_ao                  N           OFF         1000        
bb_clk2                         N           OFF         1000        
bb_clk2_ao                      N           OFF         1000        
bb_clk2_pin                     N           OFF         1000        
bb_clk2_pin_ao                  N           OFF         1000        
bimc_a_clk                      N           ON          199884800   
bimc_clk                        N           ON          120000000   200000073
bimc_msmbus_a_clk               Y           ON          680919040   
bimc_msmbus_clk                 Y           ON          120000000   
blsp1_qup1_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup1_spi_apps_clk_src     Y           OFF         0           
blsp1_qup2_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup2_spi_apps_clk_src     Y           OFF         0           
blsp1_qup3_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup3_spi_apps_clk_src     Y           OFF         0           
blsp1_qup4_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup4_spi_apps_clk_src     Y           OFF         0           
blsp1_qup5_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup5_spi_apps_clk_src     Y           OFF         0           
blsp1_qup6_i2c_apps_clk_src     Y           OFF         19200000    
blsp1_qup6_spi_apps_clk_src     Y           OFF         0           
blsp1_uart1_apps_clk_src        Y           OFF         7372800     
blsp1_uart2_apps_clk_src        Y           OFF         48000000    
blsp1_uart3_apps_clk_src        Y           OFF         0           
blsp1_uart4_apps_clk_src        Y           OFF         0           
blsp1_uart5_apps_clk_src        Y           OFF         0           
blsp1_uart6_apps_clk_src        Y           OFF         0           
blsp2_qup1_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup1_spi_apps_clk_src     Y           OFF         0           
blsp2_qup2_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup2_spi_apps_clk_src     Y           OFF         0           
blsp2_qup3_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup3_spi_apps_clk_src     Y           OFF         15000000    
blsp2_qup4_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup4_spi_apps_clk_src     Y           OFF         0           
blsp2_qup5_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup5_spi_apps_clk_src     Y           OFF         0           
blsp2_qup6_i2c_apps_clk_src     Y           OFF         19200000    
blsp2_qup6_spi_apps_clk_src     Y           OFF         0           
blsp2_uart1_apps_clk_src        Y           OFF         0           
blsp2_uart2_apps_clk_src        Y           ON          7372800     
blsp2_uart3_apps_clk_src        Y           OFF         0           
blsp2_uart4_apps_clk_src        Y           OFF         0           
blsp2_uart5_apps_clk_src        Y           OFF         0           
blsp2_uart6_apps_clk_src        Y           OFF         0           
byte0_clk_src                   Y           ON          49814910    
byte1_clk_src                   Y           OFF         19200000    
camss_ahb_clk                   Y           OFF         19200000    0
camss_cci_ahb_clk               Y           OFF         0           0
camss_cci_clk                   Y           OFF         37500000    0
camss_cpp_ahb_clk               Y           OFF         0           0
camss_cpp_axi_clk               Y           OFF         0           0
camss_cpp_clk                   Y           OFF         480000000   0
camss_cpp_vbif_ahb_clk          Y           OFF         0           0
camss_csi0_ahb_clk              Y           OFF         0           0
camss_csi0_clk                  Y           OFF         0           0
camss_csi0phy_clk               Y           OFF         0           0
camss_csi0phytimer_clk          Y           OFF         0           0
camss_csi0pix_clk               Y           OFF         0           0
camss_csi0rdi_clk               Y           OFF         0           0
camss_csi1_ahb_clk              Y           OFF         0           0
camss_csi1_clk                  Y           OFF         0           0
camss_csi1phy_clk               Y           OFF         0           0
camss_csi1phytimer_clk          Y           OFF         0           0
camss_csi1pix_clk               Y           OFF         0           0
camss_csi1rdi_clk               Y           OFF         0           0
camss_csi2_ahb_clk              Y           OFF         0           0
camss_csi2_clk                  Y           OFF         0           0
camss_csi2phy_clk               Y           OFF         0           0
camss_csi2phytimer_clk          Y           OFF         0           0
camss_csi2pix_clk               Y           OFF         0           0
camss_csi2rdi_clk               Y           OFF         0           0
camss_csi3_ahb_clk              Y           OFF         0           0
camss_csi3_clk                  Y           OFF         0           0
camss_csi3phy_clk               Y           OFF         0           0
camss_csi3pix_clk               Y           OFF         0           0
camss_csi3rdi_clk               Y           OFF         0           0
camss_csi_vfe0_clk              Y           OFF         320000000   0
camss_csi_vfe1_clk              Y           OFF         320000000   0
camss_csiphy0_3p_clk            Y           OFF         0           0
camss_csiphy1_3p_clk            Y           OFF         0           0
camss_csiphy2_3p_clk            Y           OFF         0           0
camss_gp0_clk                   Y           OFF         0           0
camss_gp0_clk_src               Y           OFF         0           
camss_gp1_clk                   Y           OFF         0           0
camss_gp1_clk_src               Y           OFF         0           
camss_ispif_ahb_clk             Y           OFF         0           0
camss_jpeg0_clk                 Y           OFF         0           0
camss_jpeg2_clk                 Y           OFF         0           0
camss_jpeg_ahb_clk              Y           OFF         0           0
camss_jpeg_axi_clk              Y           OFF         0           0
camss_jpeg_dma_clk              Y           OFF         0           0
camss_mclk0_clk                 Y           OFF         24000000    0
camss_mclk1_clk                 Y           OFF         24000000    0
camss_mclk2_clk                 Y           OFF         24000000    0
camss_mclk3_clk                 Y           OFF         19200000    0
camss_micro_ahb_clk             Y           OFF         0           0
camss_top_ahb_clk               Y           OFF         0           0
camss_vfe0_ahb_clk              Y           OFF         0           0
camss_vfe0_clk                  Y           OFF         320000000   0
camss_vfe0_stream_clk           Y           OFF         320000000   0
camss_vfe1_ahb_clk              Y           OFF         0           0
camss_vfe1_clk                  Y           OFF         320000000   0
camss_vfe1_stream_clk           Y           OFF         320000000   0
camss_vfe_ahb_clk               Y           OFF         0           0
camss_vfe_axi_clk               Y           OFF         0           0
cbf_clk                         Y           ON          1056000000  1055999963
cbf_hf_mux                      Y           ON          1593600000  134483821
cbf_pll                         Y           ON          1593600000  
cbf_pll_main                    Y           OFF         307200000   
cci_clk_src                     Y           OFF         37500000    
ce1_a_clk                       N           OFF         2147483647  
ce1_clk                         N           OFF         0           0
cnoc_a_clk                      N           ON          19200000    
cnoc_clk                        N           OFF         0           19200036
cnoc_msmbus_a_clk               Y           ON          19200000    
cnoc_msmbus_clk                 Y           OFF         250000      
cpp_clk_src                     Y           OFF         480000000   
cpu_dbg_clk                     Y           OFF         1593600000  606053143
cpu_debug_mux                   Y           OFF         1593600000  1077501110
csi0_clk_src                    Y           OFF         0           
csi0phytimer_clk_src            Y           OFF         0           
csi1_clk_src                    Y           OFF         0           
csi1phytimer_clk_src            Y           OFF         0           
csi2_clk_src                    Y           OFF         0           
csi2phytimer_clk_src            Y           OFF         0           
csi3_clk_src                    Y           OFF         0           
csiphy0_3p_clk_src              Y           OFF         0           
csiphy1_3p_clk_src              Y           OFF         0           
csiphy2_3p_clk_src              Y           OFF         0           
cxo_clk_src                     N           ON          19200000    
cxo_clk_src_ao                  N           ON          19200000    
cxo_dwc3_clk                    Y           ON          19200000    
cxo_lpm_clk                     Y           ON          1000        
cxo_otg_clk                     Y           OFF         1000        
cxo_pil_lpass_clk               Y           OFF         1000        
cxo_pil_ssc_clk                 Y           OFF         1000        
div_clk1                        N           OFF         1000        
div_clk1_ao                     N           OFF         1000        
div_clk2                        N           OFF         1000        
div_clk2_ao                     N           OFF         1000        
div_clk3                        N           OFF         1000        
div_clk3_ao                     N           OFF         1000        
dsi0pll_byte_clk_mux            Y           ON          49814910    
dsi0pll_byte_clk_src            Y           ON          49814910    
dsi0pll_n2_div_clk              Y           ON          132839760   
dsi0pll_pixel_clk_mux           Y           ON          66419880    
dsi0pll_pixel_clk_src           Y           ON          66419880    
dsi0pll_post_n1_div_clk         Y           ON          398519280   
dsi0pll_shadow_byte_clk_src     Y           OFF         0           
dsi0pll_shadow_n2_div_clk       Y           OFF         0           
dsi0pll_shadow_pixel_clk_src    Y           OFF         0           
dsi0pll_shadow_post_n1_div_clk  Y           OFF         0           
dsi0pll_shadow_vco_clk          Y           OFF         0           
dsi0pll_vco_clk_8996            Y           ON          1594077120  
dsi1pll_byte_clk_mux            Y           OFF         0           
dsi1pll_byte_clk_src            Y           OFF         0           
dsi1pll_n2_div_clk              Y           OFF         0           
dsi1pll_pixel_clk_mux           Y           OFF         0           
dsi1pll_pixel_clk_src           Y           OFF         0           
dsi1pll_post_n1_div_clk         Y           OFF         0           
dsi1pll_shadow_byte_clk_src     Y           OFF         0           
dsi1pll_shadow_n2_div_clk       Y           OFF         0           
dsi1pll_shadow_pixel_clk_src    Y           OFF         0           
dsi1pll_shadow_post_n1_div_clk  Y           OFF         0           
dsi1pll_shadow_vco_clk          Y           OFF         0           
dsi1pll_vco_clk_8996            Y           OFF         0

dtsi

./kernel/arch/arm/boot/dts/qcom/apq8096-eragon820.dtsi

#include "msm8996-pinctrl.dtsi"
#include "apq8096-camera-sensor-eragon.dtsi"
#include "msm8996-wsa881x.dtsi"
#include "msm8996-mdss-panels.dtsi"

./kernel/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi

#include "dsi-panel-sharp-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
#include "dsi-panel-nt35597-dsc-wqxga-video.dtsi"
#include "dsi-panel-jdi-dualmipi-video.dtsi"
#include "dsi-panel-jdi-dualmipi-cmd.dtsi"
#include "dsi-panel-jdi-4k-dualmipi-video-nofbc.dtsi"
#include "dsi-panel-sim-video.dtsi"
#include "dsi-panel-sim-dualmipi-video.dtsi"
#include "dsi-panel-sim-cmd.dtsi"
#include "dsi-panel-sim-dualmipi-cmd.dtsi"
#include "dsi-panel-nt35597-dsc-wqxga-cmd.dtsi"
#include "dsi-panel-hx8379a-truly-fwvga-video.dtsi"
#include "dsi-panel-r69007-dualdsi-wqxga-cmd.dtsi"
#include "dsi-adv7533-720p.dtsi"
#include "dsi-adv7533-1080p.dtsi"
#include "dsi-panel-nt35950-dsc-4k-cmd.dtsi"
#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi"
#include "dsi-panel-sharp-1080p-cmd.dtsi"
#include "dsi-panel-sharp-dsc-4k-video.dtsi"
#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
#include "dsi-panel-ssd2080m-720p-video.dtsi"
#include "dsi-panel-ortustech-720p-cmd.dtsi"

output

./out/target/product/msm8996/

wifip2p

This is where the code that sets up the search pattern for the auto p2p connection software is implemented. See the string "PERMITTED_DEVICES" in the notifyInvitationSent method. Potential modification to include a new method allowing dynamic setting from the application to configure this connection. Timing maybe important...

./frameworks/opt/net/wifi/service/java/com/android/server/wifi/p2p/WifiP2pServiceImpl.java
./frameworks/opt/net/wifi/service/java/com/android/server/wifi/p2p/WifiP2pService.java

Problems/Fixes

Build failure

Make sure you run both these commands:

source build/envsetup.sh
lunch harrier-userdebug
make clean
make -j 10

Don't forget to do the export

export LC_ALL=C

Jack server failure

error: process ID list syntax error

Usage:
 ps [options]

 Try 'ps --help <simple|list|output|threads|misc|all>'
  or 'ps --help <s|l|o|t|m|a>'
 for additional help text.

For more details see ps(1).
Port 8077 is used by another process (pid=), please ensure to free the port or change port configuration in '/home/david/.jack-settings' and '/home/david/.jack- 
server/config.properties'
error: process ID list syntax error

Fix is as follows, edit /etc/java-8-openjdk/security/java.security:

1.  I can turn on the support of TLS1.0/1.1 manually by removing the TLSv1, TLSv1.1 declaring in jdk.tls.disabledAlgorithms configuration in file /etc/java-8-openjdk/security/java.security.
2.  Switch to use TLS1.2 for the build system.

repo/kernel change info

=== repo and git commands

~/bin/repo sync -c --no-clone-bundle
git branch -a

cd device/viken
git switch heuresis-bitbucket/disea/viken/LA.UM.6.5.r1-06000-8x96.0
git checkout --track remotes/heuresis-bitbucket/disea/viken/LA.UM.6.5.r1-06000-8x96.0
git fetch
git pull
cd ../../kernel/msm-3.18
git switch heuresis-bitbucket/disea/viken/LA.UM.6.5.r1-06000-8x96.0
git checkout --track remotes/heuresis-bitbucket/disea/viken/LA.UM.6.5.r1-06000-8x96.0
git fetch
git pull

branches

viken/LA.UM.6.5.r1-06000-8x96.0
remotes/heuresis-bitbucket/Rel_V3.0
remotes/heuresis-bitbucket/disea/viken/LA.UM.6.5.r1-06000-8x96.0
remotes/heuresis-bitbucket/feat/ili9881d-support/viken/LA.UM.6.5.r1-06000-8x96.0
remotes/heuresis-bitbucket/feat/ili9881d-test-mode/viken/LA.UM.6.5.r1-06000-8x96.0
remotes/heuresis-bitbucket/heuresis/LA.UM.6.5.r1-06000-8x96.0_Rel_V3.0
remotes/heuresis-bitbucket/viken/LA.UM.6.5.r1-06000-8x96.0
remotes/m/heuresis/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/heuresis/LA.UM.6.5.r1-06000-8x96.0_Rel_V3.0
remotes/m/viken/LA.UM.6.5.r1-06000-8x96.0 -> heuresis-bitbucket/viken/LA.UM.6.5.r1-06000-8x96.0

bootanimation

Make the jpg's

fmpeg -i ../Raven-splash-091624.mp4 -vf fps=30 -s 720x405 out%d.jpg

edit the desc.txt file

720 405 30
p 1 0 part0 FFFFFF

zip the animation

zip -r0 bootanimation.zip part0 desc.txt

copy to kernel location

cp bootanimation.zip /mnt/data/projects/snap/device/viken/harrier

Snapdragon target board

kernel/msm-3.18/arch/arm64/boot/dts/qcom/apq8096-hbi160.dtsi

I2C

/sys/class/gpio element
gpiochip0 1010000.pinctrl
gpiochip1005 pmi8994-mpp
gpiochip1006 pmi8994-gpio
gpiochip1010 pm8994-mpp
gpiochip1012 pm8994-gpio
gpiochip389 rdbg
gpiochip421 rdbg
gpiochip453 rdbg
gpiochip485 rdbg
gpiochip517 master-kernel
gpiochip549 slave-kernel
gpiochip581 master-kernel
gpiochip613 slave-kernel
gpiochip645 master-kernel
gpiochip677 slave-kernel
gpiochip709 sleepstate
gpiochip741 smp2p
gpiochip773 smp2p
gpiochip805 smp2p
gpiochip837 smp2p
gpiochip869 smp2p
gpiochip901 smp2p
gpiochip933 smp2p
gpiochip965 smp2p
gpiochip997 pca9557

gpio devices

The individual gpio's won't exist until they are created or exported.

echo 986 > /sys/class/gpio/export
echo out > /sys/class/gpio/gpio986/direction
echo 1 > /sys/class/gpio/gpio986/value
write /sys/class/gpio/export 986
write /sys/class/gpio/gpio986/direction "out"
write /sys/class/gpio/gpio986/value 0

This will create the /sys/class/gpio/gpio986/ entry to allow for pin control. Also shown is setting the direction and value for the pin.

graphics frame buffers

ls /sys/devices/virtual/graphics/fb0  (or fb1)

Fastboot

make updatepackage
fastboot devices
fastboot format userdata
fastboot flash userdata <userdata>.img
fastboot update <img>.zip

Networking

To get the ethernet working on the snapdragon you must:

  • connect to a wifi network (otherwise the WifiP2P software doesn't get an intent to start the server)
  • connect up an ethernet cable
  • logon to the snapdragon via usb
  • verify eth0 is up
  • issue this command "ifconfig eth0:1 192.168.1.12 netmask 255.255.255.0 up"

PCIe

[1] generic pci driver

[2] paper on memory mapping pci

[3] interesting search for pci memory map options (includes uio_pci_generic)

Code lives in "./kernel/msm-3.18/drivers/uio"

Useful commands

lspci -k
ls /sys/class/uio
ls /sys/bus/pci

Vendor Id 0x1172 Class Code 0x00058000

harrier:/ $ lspci -k                                                           
00:00.0 Class 0604: 17cb:0104
01:00.0 Class 0280: 168c:003e cnss_wlan_pci
00:00.0 Class 0604: 17cb:0104
01:00.0 Class 0604: 10b5:8604
02:01.0 Class 0604: 10b5:8604
02:04.0 Class 0604: 10b5:8604
02:05.0 Class 0604: 10b5:8604
<span style="background:yellow">03:00.0 Class 0580: 1172:0000</span>
04:00.0 Class 0200: 1969:1083 atl1c

Loaded drivers:

harrier:/ $ ls -l /sys/bus/pci/drivers                                         
total 0
drwxr-xr-x 2 root root 0 2020-03-26 11:33 atl1c
drwxr-xr-x 2 root root 0 2020-03-26 11:33 cnss_wlan_pci
drwxr-xr-x 2 root root 0 2020-03-26 11:33 dwc3-pci
drwxr-xr-x 2 root root 0 2020-03-26 11:33 ehci-pci
drwxr-xr-x 2 root root 0 2020-03-26 11:33 mhi_pcie_drv
drwxr-xr-x 2 root root 0 2020-03-26 11:33 xhci_hcd

Resource file:

cat /sys/bus/pci/devices/0002\:03\:00.0/                          (or)
cat /sys/class/pci_bus/0002\:03/device/0002\:03\:00.0/resource     
0x000000000e400000 0x000000000e400fff 0x000000000014220c
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x000000000e800000 0x000000000effffff 0x000000000014220c
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000

[4] uio_pci_generic mod to support memory mapping

[5] issue mapping resource0 file

[6] arm64 add support for pci_mmap_page_range

This last link got the resource0 files to show up adding in the pci_mmap_page_range. Things still crash badly when I access, but I just need to test a single word read and see if that works.

Modify system boot config, remove uio_pci_generic driver config

adb root
adb disable-verity
adb reboot
adb root
adb remount
adb shell mv /system/etc/uio_pci_setup.sh /system/etc/uio_pci_setup.sh.bak
adb shell sync
adb reboot

Now with Rich's latest fpga

cat resource                                                                                                           <
0x000000000e540000 0x000000000e543fff 0x000000000014220c
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x000000000e500000 0x000000000e53ffff 0x000000000014220c
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000

Running the kynetics test app yeilds:

2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[0] = 0xdeadbeef
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[1] = 0xdcba0040
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[2] = 0x7091246
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[3] = 0x196f0020
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[4] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[5] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[6] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[7] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[8] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[9] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[10] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[11] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[12] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[13] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[14] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[15] = 0x0
2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[16] = 0x0

Notes from Rich's email July 9, 2020

The memory that I have provided for the PCIE interface is:

Memory 1:          BAR0 Configuration/monitor/status memory 16384 bytes or from your end 2048 64bit words
                   Address 0000_0000   0000_3fff
Memory 2:          BAR2 Data buffers  -  262144 bytes or from you end 32768 -  64bit words
                   Address 0000_0000    0003_ffff  

Configuration/monitor/status Memory addressing (16 bit data word):

               Address 0 byte 1/0           <=           whoami;  “beef”
               Address 0 byte 3/2           <=           reg_ver;  “dead”
               Address 0 byte 5/4           <=           brd_ver;  ?
               Address 0 byte 7/6           <=           16'hdcba;
               Address 1 byte 1/0           <=           comp_time;       ‘h1246
               Address 1 byte 3/2           <=           comp_date;       ‘h0709
               Address 1 byte 5/4           <=           comp_year;        ‘h0020
               Address 1 byte 7/6           <=           time_date;         ‘h196f  (I think)

The following memory locations have the data pointers for the last memory location written to. Address 2 byte 1/0 <= pcie_mem2_wr_pntr_a[15:0];

               Address 2 byte 3/2           <=           pcie_mem2_wr_pntr_a[31:16];
               Address 2 byte 5/4           <=           pcie_mem2_wr_pntr_b[15:0]:
               Address 2 byte 7/6           <=           pcie_mem2_wr_pntr_b[31:16];

Address 3 byte 1/0 <= pcie_mem2_wr_pntr_c[15:0];

               Address 3 byte 3/2           <=           pcie_mem2_wr_pntr_c[31:16];
               Address 3 byte 5/4           <=           pcie_mem2_wr_pntr_d[15:0]:
               Address 3 byte 7/6           <=           pcie_mem2_wr_pntr_d[31:16];

CPU info

cat /proc/cpuinfo
cat /sys/devices/virtual/thermal/thermal_zone?/temp
cat /sys/devices/system/cpu/cpu?/cpufreq/cpuinfo_max_freq