Editing Xrf spi debug (section)

== Register definitions ==

{| align="&quot;center" border="&quot;1&quot;"
! register
! description
|-
| REG_ADDR_0 || Frequency value (set to 9?) Might readback some testscope2 block data
|-
| REG_ADDR_1 || Delay value (set to 20?), bit 15 something to do with scope data
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| REG_ADDR_2 || shaper control
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| || bit 11 unused, bit 10 rtd shaper enable, bit 9 slow shaper enable, bit 8 fast shaper enable
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| || bit 7 rtd enable, bit 6 unused, bit 5 unused, bit 4 start timer (appears to be disconnected in 8474)
|-
| || bit 3 unused, bit 2 unused, bit 1 enable acquisition (and timers), bit 0 reset blr
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| REG_ADDR_3 || Revision register (DD[3][15..0]
|-
| REG_ADDR_4 || Live Time LSB &lt;code&gt;GetCurrentRealAndLiveTime&lt;/code&gt;  Pulse processor state machine is halted until these are non-zero.  These values should be initialized to 0xffff and this will allow the pulse processor to run.  (countdown).
|-
| REG_ADDR_5 || Live Time MSB &lt;code&gt;GetCurrentRealAndLiveTime&lt;/code&gt;  Pulse processor state machine is halted until these are non-zero.  These values should be initialized to 0xffff and this will allow the pulse processor to run.  (countdown).
|-
| REG_ADDR_6 || Real Time LSB &lt;code&gt;GetCurrentRealAndLiveTime&lt;/code&gt;  Pulse processor state machine is halted until these are non-zero.  These values should be initialized to 0xffff and this will allow the pulse processor to run.  (countdown).
|-
| REG_ADDR_7 || Real Time MSB &lt;code&gt;GetCurrentRealAndLiveTime&lt;/code&gt;  Pulse processor state machine is halted until these are non-zero.  These values should be initialized to 0xffff and this will allow the pulse processor to run.  (countdown).
|-
| REG_ADDR_8 || Live Time LSB &lt;code&gt;GetRealAndLiveTime&lt;/code&gt; (latched values)
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| REG_ADDR_9 || Live Time MSB &lt;code&gt;GetRealAndLiveTime&lt;/code&gt; (latched values)
|-
| REG_ADDR_10 || Real Time LSB &lt;code&gt;GetRealAndLiveTime&lt;/code&gt; (latched values)
|-
| REG_ADDR_11 || Real Time MSB &lt;code&gt;GetRealAndLiveTime&lt;/code&gt; (latched values)
|-
| REG_ADDR_12 || Current fast value (read only)
|-
| REG_ADDR_13 || Current slow value (read only)
|-
| REG_ADDR_14 || unused
|-
| REG_ADDR_15 || unused
|-
| REG_ADDR_16 || adc offset
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| REG_ADDR_17 || gate width extension
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| REG_ADDR_18 || gate recovery
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| REG_ADDR_19 || bits 0-7 fast rise time, bits 8-15 fast flat top + fast rise time
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| REG_ADDR_20 || bit 15 cusp trap, 0-14 slow flat top
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| REG_ADDR_21 || slow rise time
|-
| REG_ADDR_22 || bits 0-7 slow extension, bits 8-15 fast extension
|-
| REG_ADDR_23 || fast threshold low, typically set to 1.5*current fast value
|-
| REG_ADDR_24 || fast threshold high, typically set to 2.0*current fast value
|-
| REG_ADDR_25 || slow threshold low, typically set to 1.5*current slow value
|-
| REG_ADDR_26 || slow threshold high, typically set to 2.0*current slow value
|-
| REG_ADDR_27 || bits 0-7 slow blr tau, bits 8-15 fast blr tau
|-
| REG_ADDR_28 || after peak guard
|-
| REG_ADDR_29 || peak time
|-
| REG_ADDR_30 || fpga gain, gain control (00-&gt;gain=1.05, 01 -&gt;gain=2, 02 -&gt; gain=4)
|-
| REG_ADDR_31 || slow bin gain
|-
| REG_ADDR_32 || slow fine gain
|-
| REG_ADDR_33 || dt extension
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| REG_ADDR_34 || rtd rise time
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| REG_ADDR_35 || rtd flat top rtm
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| REG_ADDR_36 || bit 0 Bank select (0=bank_0, 1=bank_1), bit 1 clear on read (0=clear, 1=no clear)
|-
| REG_ADDR_37 ||
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| REG_ADDR_38 ||
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| REG_ADDR_39 ||
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| REG_ADDR_40 ||
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| REG_ADDR_41 ||
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| REG_ADDR_42 ||
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| REG_ADDR_43 ||
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| REG_ADDR_44 ||
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| REG_ADDR_45 ||
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| REG_ADDR_46 ||
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| REG_ADDR_47 ||
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| REG_ADDR_48 ||
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| REG_ADDR_49 ||
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| REG_ADDR_50 ||
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| REG_ADDR_51 ||
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| REG_ADDR_52 ||
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| REG_ADDR_53 ||
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| REG_ADDR_54 ||
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| REG_ADDR_55 ||
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| REG_ADDR_56 ||
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| REG_ADDR_57 ||
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| REG_ADDR_58 ||
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| REG_ADDR_59 ||
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| REG_ADDR_60 ||
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| REG_ADDR_61 ||
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| REG_ADDR_62 ||
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| REG_ADDR_63 ||
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| REG_ADDR_64 ||
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| REG_ADDR_65 ||
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| REG_ADDR_66 ||
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| REG_ADDR_67 ||
|-
| REG_ADDR_68 ||
|-
| REG_ADDR_69 ||
|}

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