Editing Build android snapdragon (section)

== I2C bus config info ==

The dtsi file is located:

 kernel/msm-3.18/arch/arm/boot/dts/qcom/apq8096-hbi160.dtsi

I2c-10 is set to 100k baud rate.  This should be the location of the summing box fpga at address 0x55.

Just added the following parameters to the dtsi file making the duty cycle actually 50% not 30% @100kHz based on the default settings.

 /* modified from standard values
    fs-clk-div = 124
    high-time-clk-div = 62
    The following values where determined empirically to achieve a 50%
    duty cycle on the clk.
    */
 qcom,fs-clk-div = &lt;90&gt;;
 qcom,high-time-clk-div = &lt;93&gt;;
 /* 0x0 – Legacy mode
    0x01 – One cycle wide low pulse is rejected
    0x2 – Two cycles wide low pulse is rejected
    0x3 – Three cycles wide low pulse is rejected
    */
 qcom,noise-rjct-scl = &lt;0&gt;;
 qcom,noise-rjct-sda = &lt;0&gt;;