Editing Snapdragon (section)

=== Now with Rich's latest fpga ===

 cat resource                                                                                                           &lt;
 0x000000000e540000 0x000000000e543fff 0x000000000014220c
 0x0000000000000000 0x0000000000000000 0x0000000000000000
 0x000000000e500000 0x000000000e53ffff 0x000000000014220c
 0x0000000000000000 0x0000000000000000 0x0000000000000000
 0x0000000000000000 0x0000000000000000 0x0000000000000000
 0x0000000000000000 0x0000000000000000 0x0000000000000000
 0x0000000000000000 0x0000000000000000 0x0000000000000000

Running the kynetics test app yeilds:

 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[0] = 0xdeadbeef
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[1] = 0xdcba0040
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[2] = 0x7091246
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[3] = 0x196f0020
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[4] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[5] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[6] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[7] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[8] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[9] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[10] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[11] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[12] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[13] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[14] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[15] = 0x0
 2020-10-13 11:10:34.275 3554-3554/com.viken.pcietest I/pcieLib: data[16] = 0x0

Notes from Rich's email July 9, 2020

The memory that I have provided for the PCIE interface is:

 Memory 1:          BAR0 Configuration/monitor/status memory 16384 bytes or from your end 2048 64bit words
                    Address 0000_0000   0000_3fff
 Memory 2:          BAR2 Data buffers  -  262144 bytes or from you end 32768 -  64bit words
                    Address 0000_0000    0003_ffff  

Configuration/monitor/status Memory addressing (16 bit data word):

                Address 0 byte 1/0           &lt;=           whoami;  “beef”
                Address 0 byte 3/2           &lt;=           reg_ver;  “dead”
                Address 0 byte 5/4           &lt;=           brd_ver;  ?
                Address 0 byte 7/6           &lt;=           16'hdcba;
                Address 1 byte 1/0           &lt;=           comp_time;       ‘h1246
                Address 1 byte 3/2           &lt;=           comp_date;       ‘h0709
                Address 1 byte 5/4           &lt;=           comp_year;        ‘h0020
                Address 1 byte 7/6           &lt;=           time_date;         ‘h196f  (I think)

The following memory locations have the data pointers for the last memory location written to.
Address 2 byte 1/0           &lt;=           pcie_mem2_wr_pntr_a[15:0];  
                Address 2 byte 3/2           &lt;=           pcie_mem2_wr_pntr_a[31:16];
                Address 2 byte 5/4           &lt;=           pcie_mem2_wr_pntr_b[15:0]:
                Address 2 byte 7/6           &lt;=           pcie_mem2_wr_pntr_b[31:16];
Address 3 byte 1/0           &lt;=           pcie_mem2_wr_pntr_c[15:0];
                Address 3 byte 3/2           &lt;=           pcie_mem2_wr_pntr_c[31:16];
                Address 3 byte 5/4           &lt;=           pcie_mem2_wr_pntr_d[15:0]:
                Address 3 byte 7/6           &lt;=           pcie_mem2_wr_pntr_d[31:16];