Editing Xrf spi debug (section)

=== Setting of Shapers ===

<code>InitShaperXL3</code> sets up a local structure with shaper parameters based on the current detector being used.  This function also calls <code>adjustDetectorShapers</code> and <code>SetShaperXL3</code>.  This function then terminates.

<code>adjustDetectorShapers</code> modify's some of the parameters based on a few more conditions.  Why this is not included in the previous function is beyond me...  All parameters are in system ram, still nothing has been updated in the actual fpga registers.

<code>SetShaperXL3</code> makes some addition modifications to parameters and creates a few new ones based on other but with additional offsets (wtf), it then calls <code>SetShaperUsingSPI</code>.  There is also the ability to debug output a collection of probably important parameters:
<pre>
sprintf(buf,&quot;SLOW_RISE_TIME:%d\r\n&quot;,SHS.SLOW_RISE_TIME);
sprintf(buf,&quot;GATE_RECOVERY:%d\r\n&quot;,SHS.GATE_RECOVERY);
sprintf(buf,&quot;RTD_RISE_TIME:%d\r\n&quot;,SHS.RTD_RISE_TIME);
sprintf(buf,&quot;RTD_FLAT_TOP_RTM:%d\r\n&quot;,SHS.RTD_FLAT_TOP_RTM);
sprintf(buf,&quot;PEAK_TIME:%d\r\n&quot;,SHS.PEAK_TIME);
sprintf(buf,&quot;AFTER_PEAK_GUARD:%d\r\n&quot;,SHS.AFTER_PEAK_GUARD);
sprintf(buf,&quot;DT_EXTENSION:%d\r\n&quot;,SHS.DT_EXTENSION);
sprintf(buf,&quot;SLOW_EXTENSION:%d\r\n&quot;,SHS.SLOW_EXTENSION);
sprintf(buf,&quot;FAST_EXTENSION:%d\r\n&quot;,SHS.FAST_EXTENSION);
sprintf(buf,&quot;SLOW_BIN_GAIN:%d\r\n&quot;,SHS.SLOW_BIN_GAIN);
sprintf(buf,&quot;SLOW_FINE_GAIN:%d\r\n&quot;,SHS.SLOW_FINE_GAIN);
</pre>

<code>SetShaperUsingSPI</code>, I found something that actually writes stuff to the fpga.  We start off reading <code>REG_ADDR_2</code> and clearing bit 8.

<pre>
	usDetector = Read_Single ( (REG_ADDR_2) );
	usDetector &amp;= ~(1&lt;&lt;8); // First detector

	Write_Single( (REG_ADDR_2),usDetector );
	Write_Single( (REG_ADDR_17),SHS.GATE_WIDTH_EXT);
	Write_Single( (REG_ADDR_18),SHS.GATE_RECOVERY);
	Write_Single( (REG_ADDR_16),SHS.ADC_OFFSET);
	Write_Single( (REG_ADDR_19),SHS.FAST_RISE_TIME +256*(SHS.FAST_RISE_TIME+SHS.FAST_FLAT_TOP))  ;


	if (SHS.CUSP_TRAP) 
	{
		usReg7 = ((short)(SHS.SLOW_FLAT_TOP))|0x8000;
	}
	else 
	{
		usReg7 = ((short)(SHS.SLOW_FLAT_TOP))&amp;0x7FFF;
	}
	
	//bits 12 to 10 which have been moved to a new register Reg 31 
	
     Write_Single( (REG_ADDR_20), usReg7);	
     Write_Single( (REG_ADDR_21) ,SHS.SLOW_RISE_TIME);         
     Write_Single( (REG_ADDR_22) ,SHS.SLOW_EXTENSION + 256*SHS.FAST_EXTENSION);// check it with the old one and send
     Write_Single( (REG_ADDR_23),SHS.FAST_THRESH_LOW);
     Write_Single( (REG_ADDR_24),SHS.FAST_THRESH_HIGH);
     Write_Single( (REG_ADDR_25),SHS.SLOW_THRESH_LOW);
     Write_Single( (REG_ADDR_26),SHS.SLOW_THRESH_HIGH);     
     Write_Single( (REG_ADDR_27),SHS.SLOW_BLR_TAU + 256*SHS.FAST_BLR_TAU); 
     Write_Single( (REG_ADDR_28),SHS.AFTER_PEAK_GUARD );
     Write_Single( (REG_ADDR_29),SHS.PEAK_TIME);   
     Write_Single( (REG_ADDR_30),FPGA_GAIN);        // for gain control (00-&gt;gain=1.05, 01 -&gt;gain=2, 02 -&gt; gain=4) 
     Write_Single( (REG_ADDR_31),SHS.SLOW_BIN_GAIN);     
     Write_Single( (REG_ADDR_32),SHS.SLOW_FINE_GAIN); 
     Write_Single( (REG_ADDR_33),SHS.DT_EXTENSION);	
	
#if 1//def RTD    
   usReg34 = SHS.RTD_RISE_TIME;
    Write_Single(REG_ADDR_34, usReg34);// Setting the RTD RISE TIME
    usReg35 = SHS.RTD_FLAT_TOP_RTM;//usReg34 + ( usReg19 &amp; 0xFF) + ( usReg19/256 );
    Write_Single(REG_ADDR_35, usReg35);
#endif
    //Clear Spectrum is optional here
	ClearSpectrum_SPI ( );
    
    usTempData =  Read_Single ( (REG_ADDR_2) );
    usTempData &amp;= ~0x0002; //Disable acquisition
    Write_Single ( (REG_ADDR_2), usTempData ); 
    
    usTempData =  Read_Single ( (REG_ADDR_2) );
    usTempData |= (1&lt;&lt;7); //Enable RTD

   Write_Single ( (REG_ADDR_2), usTempData | 0x0000 );// This selects Slow Shaper at the output of the DAC board - default
</pre>